All-Spiking ECG Analysis for Arrhythmia Classification on Low-Power FPGA
Early detection of arrhythmias requires continuous, high-fidelity electrocardiogram (ECG) monitoring through wearable devices suitable for everyday use. However, the monitoring faces strict computational and power constraints.
Event-driven approaches such as Spiking Neural Networks (SNNs) are particularly well-suited to address these limitations. They adapt well to physiological signals like ECG, which are inherently sparse and characterized by transient, high-information features such as QRS complexes. To fully exploit the advantages of spike-driven computation and the available sparsity, Field Programmable Gate Arrays (FPGAs) offer great flexibility in allocating the necessary control and data-crunching logic.
This work introduces a lightweight SNN-based architecture for real-time ECG analysis. It integrates peak detection and arrhythmia classification into a single, fully event-driven processing pipeline, executed on spikes generated by delta-modulated encoding of the EGC signal. This solution removes the need for additional filtering stages, enabling efficient logic reuse and low-power classification on resource-constrained, low-end FPGAs suitable for wearable devices, such as the Lattice iCE40-UltraPlus.
The system is trained and evaluated primarily on the MIT-BIH Arrhythmia Database, targeting five different arrhythmia classes (N, S, V, F, Q). A 4-layer dense SNN performs peak detection to identify the QRS complex, which a second model then classifies. Data augmentation techniques, including window shifting around heartbeat peaks, are employed to reduce the impact of class imbalance, particularly for rare arrhythmia classes.
Experimental results demonstrate strong performance. Peak detection shows 99.0% positive predictive value (PPV) and 98.1% true positive rate (TPR). The arrhythmia classification system achieves 98.4% accuracy, with 88.11% sensitivity, 97.66% specificity, and an F1 score of 88.6, using 8-bit precision weights to reduce the model’s memory requirements. Noise-aware training using the MIT-BIH Noise Stress Test Database further increases robustness under challenging signal conditions, while experiments on the MIT-BIH Atrial Fibrillation Database demonstrate the general applicability of the proposed approach.
The classification system was deployed on the Lattice iCE40 UltraPlus FPGA using the open-source SYNtzulu neuromorphic processor. The architecture integrates a lightweight RISC-V controller with a dedicated SNN accelerator that can execute both peak-detection and classification networks through efficient context switching.
By reusing hardware resources and embedding encoding, inference, and decoding on-chip entirely, the design minimizes memory usage, logic utilization, and power consumption while maintaining real-time operation. The classifier requires only 4.05 ms to classify each heartbeat, whereas the peak detector completes inference in approximately 0.04 ms, thanks to significant sparsity, yielding up to 85% savings on average.
Power analysis shows that inference execution on SYNtzulu consumes an average of 9.1 mW, requiring only 36.86 μJ per heartbeat classification, outperforming previously reported FPGA-based SNN solutions in energy efficiency, all while operating on a significantly smaller device. Although dedicated ASIC implementations remain more energy-efficient, the proposed FPGA architecture offers crucial advantages of reconfigurability and accessibility.
Overall, this study demonstrates that a fully spike-driven ECG processing pipeline can achieve state-of-the-art arrhythmia detection accuracy while meeting the strict power and latency requirements of wearable healthcare devices, making it a promising solution for continuous, real-time cardiac monitoring.